Embodiments relate to a semiconductor device and a method of manufacturing a device that may maximize the reliability of the device. It may be desirable to minimize the size of a transistor allowing the number of transistors on a given area to be maximized. However, when minimizing the size of a transistor there is a limit in reducing the junction depth of the source/drain.
When manufacturing a semiconductor device, as a channel is changed from a relatively long channel to a short channel of 0.5 μm or less, a depletion region of the source/drain may penetrate the channel. This may minimize the effective channel length and threshold voltage, thereby causing a short channel effect. This short channel effect may result in a loss of gate control function in a MOS transistor.
It may be desirable to minimize the thickness of the gate insulating film or to minimize the width of the depletion region below the channel between the source/drain (e.g., a gate electrode) to minimize the short channel effect. It may also be desirable to decrease an impurity density in a semiconductor substrate and also to form a shallow junction to minimize the short channel effect.
A semiconductor device including a MOS transistor having a shallow junction is an example of a light doped drain (LDD) structure. Example FIGS. 1A to 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device.
As illustrated in example FIG. 1A, an active region and a device isolation region may be defined in semiconductor substrate 21. Device isolation film 22 may formed in the device isolation region of semiconductor substrate 21 through a LOCOS or shallow trench isolation (STI) process. After semiconductor substrate 21 is thermally oxidized at a relatively high temperature, gate insulating film 23 is deposited on and/or over semiconductor substrate 21. Then, a polysilicon layer may be deposited on and/or over the semiconductor substrate 21. Then the polysilicon layer and gate insulating film 23 may be selectively etched through a photolithography process, thereby forming gate electrode 24.
As illustrated in example FIG. 1B, oxide film 25 may be formed on and/or over the surface of semiconductor substrate 21 including gate electrode 24. Low-density impurity ions may then be injected into the surface of semiconductor substrate 21 using gate electrode 24 as a mask. Injecting impurity ions may form lightly doped drain (LDD) region 26 in the surface of semiconductor substrate 21 at the opposite sides of gate electrode 24. A low dose implant process may be used in the ion injection process.
As illustrate in example FIG. 1C, after oxide film 25 is removed, first insulating film 27 may be formed on and/or over the surface of semiconductor substrate 21 including gate electrode 24. Insulating film 28, having a different etching selectivity, may then be formed on and/or over semiconductor substrate 21. In embodiments, first insulating film 27 may be formed of a silicon oxide film and second insulating film 28 may be formed of a silicon nitride film. When oxide film 25 is removed it may influence the quality of gate insulating film 23 and maximize a divot depth of device isolation film 22. This, in turn, may influence the device performance.
As illustrated in example FIG. 1D, an etch back process may then be performed on the entire surfaces of first insulating film 27 and second insulating film 28. First insulating film sidewall 27a and second insulating film sidewall 28a may thus, be formed at the opposite side surfaces of gate electrode 24.
As illustrated in example FIG. 1E, high-density impurity ions may then be injected into the entire surface of semiconductor substrate 21 using gate electrode 24, first insulating film sidewall 27a and second insulating sidewall 28a as masks, thereby forming source/drain impurity region 29 in the surface of semiconductor substrate 21. Source/drain impurity region 29 may be formed connected to LDD region 26. In embodiments, a high dose implant process may be used in the ion injection process. An interlayer insulating film and metal lines may then be formed through a general process, thereby completing a logic process.
In such a semiconductor manufacturing method, however, the LDD region may be formed through the low dose implant process after the gate electrode is formed and through the high dose implant process after the spacer is formed. This may result in the LDD region overlapping with a lower portion of the gate insulating film as in a region OL as illustrated in example FIG. 1E. Accordingly, the overlapping LDD region and gate insulating film may deteriorate gate-induced drain leakage (GIDL) characteristics and generate a parasitic resistance that may minimize device performance.
Further, when using a spacer to create an isolation structure between the gate and active regions, there may be limitations to applying a gap-fill process to a dielectric layer between neighboring gate electrodes. Accordingly, as illustrated in example FIG. 2, defects such as a void may occur due to relatively small process variation.
As illustrated in example FIG. 2, void 30 may be formed in dielectric layer 40 between neighboring gate electrodes 24a and 24b. A W-bridge may occur between filled metal patterns due to the void.